1. Field of the Invention
This invention is in the field of semiconductor devices and is directed particularly to thyristors, and especially to (GTO) thyristors.
2. Description of Prior Art
In general, thyristors are four layer, P-N-P-N structures considered to be comprised of a P-N-P and an N-P-N transistor with the two central regions being common to both transistors. The thyristor is held in the "on-state" by driving the two interior or base regions.
GTO thyristors are thyristors designed to go from the "on-state" to the "off-state" by withdrawing current from one of the base regions.
With reference to FIG. 1, there is shown a longitudinal cross-sectional schematical view of a conventional (GTO) thyristor.
A typical manufacturing process would comprise a P+ type emitter layer (10) being formed on a first main face of an N.sup.- silicon substrate which eventually constitutes a base layer (12) of the thyristor by diffusion. Then a P type base layer (14) being formed in a predetermined portion of a second main face of the N.sup.- type base layer (10) by diffusion. An N.sup.+ type emitter layer (16) being formed which extends from the surface of that P type base layer (14) into the interior thereof.
Subsequently, after an insulating film (18) used as a mask for forming the N.sup.+ type emitter layer (16) has been windowed, an anode electrode (20), gate electrodes (22) and a cathode electrode (24) are formed by conventional methods.
An important parameter for thyristors is turn-off gain (G.sub.off). Turn-off gain indicates how much current (I.sub.G) is required to be drawn from the base region to turn the principal current (I.sub.A) off. In order to render electric power consumed by the gate circuit low, it is necessary to decrease the drawn (I.sub.G) and increase the (G.sub.off). Assuming that .alpha..sub.p and .alpha..sub.n designate respectively current amplification degrees of the PNP and NPN transistors, formed by regions 10-12-14 and regions 16-14-12 respectively which are the elements comprising the GTO thyristor, (G.sub.off) is expressed by the equation: EQU G.sub.off =I.sub.A /I.sub.G =.alpha..sub.n /(.alpha..sub.p +.alpha..sub.n -1).
More specifically, and as can be seen from the above equation, increasing the (G.sub.off) decreases the .alpha..sub.n and .alpha..sub.p and causes .alpha..sub.n +.alpha..sub.p to approximate 1. In prior art in order to decrease .alpha..sub.p, gold doping has been used. Also the P type base layer (14) has been thickened and its impurity concentration made higher in order to make the .alpha..sub.n small but then an "on-state" voltage becomes high and forward voltage drop increases. Further a loss due to the "turn-off" increases. In order to make the "on-state" voltage low, the .alpha..sub.n is more or less increased. Namely, when the P type base layer (14) is thinned and its impurity concentration is lowered, the P type base layer (14) increases in lateral resistance resulting in the (GTO) thyristor being difficult to "turn off" and an increased switching loss is realized.
In order to prevent the lateral resistance of P- type base region (14) from increasing, or at least to minimize any increase in lateral resistance, there was developed a (GTO) thyristor of the type shown in FIG. 2. The same numbers have been used in FIG. 2 as in FIG. 1 to denote similar or like regions and electrodes.
In the (GTO) thyristor shown in FIG. 2 gate electrode (22) is digitized or striped on P type base layer (14) to prevent the lateral resistance of the P type base layer (14) from increasing. Thus the "turn-off" time is shortened.
However, in order to further reduce the "turn-off" time of the (GTO) thyristor, it is required to further lower the lateral resistance of region 14 by decreasing the width or spacing of the gate electrode 22. This has decreased the yield due to pattern defects in the photoengraving step.